The present invention relates to a system and apparatus for correcting/detecting data error of a memory device, and more particularly to a system and apparatus for reliably correcting/detecting data error of a memory device even if the memory device is constructed of IC memory packages having different input/output data bit numbers.
Generally, a memory device, using IC memory packages (chips) has been constructed having a number of IC memory packages of one-bit input/output data structure, in order to improve integration density by reducing the number of pins on an IC memory package. However, as recent IC memories are becoming highly integrated, IC memory packages of b bit input/output data structure (b is an integer of 3 or larger, e.g., b=4) are often used. A memory device using IC memory packages of b bit input/output data structure has the following problem. Namely, even if one of the IC memory packages becomes faulty, there is a possibility of multiple bit errors within an n bit block outputted from the faulty IC package.
Recently, a method of correcting/detecting data error of such a memory device has been proposed which uses SEC-DED-SbED codes (Single Error Correcting-Double Error Detecting-Single (b) bit byte Error Detecting codes) allowing to correct on bit error, detect two bit errors, and detect three or more bit errors within the same b bit block.
Such conventional error correcting/detecting methods are known for example as:
(1) a method using codes disclosed in a paper entitled "Byte Error Detecting Code for Semiconductor Memory Device" by Kaneda, written in one of the papers Vol.J67-D No.5, May, 1984, of The Institute of Electronics and Communication Engineers of Japan, and PA1 (2) a method using codes disclosed in JP-A-6-139846 or other publications, these codes being constructed by rotating a b=b matrix by an optional number (g) of bits in the column direction and by consecutively placing sub-matrices.
A memory device using a plurality of IC memory packages according the conventional technique is beginning to have a problem of too large a minimum unit of memory capacity, because a more recent IC memory package has a large capacity and high integration (current integration rate is about four times in three years).
In order to solve such a problem, a memory device has been proposed which uses IC memory packages of multiple bit input/output data structure so that the number of IC packages of the memory device can be reduced and the minimum unit of memory capacity can be prevented from becoming too large. However, such a memory device has a high possibility of generation of multiple bit errors if one IC memory package becomes faulty. An ability to detecting such multiple bit errors has not been considered in spite of memory expansion by the generation change of IC packages. It is therefore difficult to reliably deal with the generation change of IC memory packages. This point will be further discussed with reference to FIG. 5.
FIG. 5 is a diagram showing an example of a conventional memory expansion method.
A memory device is assumed to be constructed as having a 4-byte (32 bits) data width for example as shown in FIG. 5.
If a memory device is constructed of IC memory packages of one-bit input/output data structure, it is necessary to allow correction of one bit error and detection of two bit errors. Seven check bits are therefore required. The total code length of the memory device becomes 39 bits, and so the memory device can be constructed using thirty nine IC memory packages.
In this case, if thirty-nine 1 mega .times.1 bit dynamic RAM (hereinafter called DRAM) packages of the first generation are used as IC memory packages, the minimum unit of memory capacity of the memory device becomes 4 megabytes (MB). Similarly, if thirty nine 4 M .times.1 bit DRAM packages of the second generation are used, the minimum unit of memory capacity of the memory device becomes 16 MB. If thirty nine 16 M.times.1 bit DRAM packages of the third generation are used, the minimum unit of memory capacity of the memory device becomes 64 MB. In this manner, use of IC memory packages of one-bit input/output structure of each generation results in a large minimum unit of memory capacity of the memory device.
In general, the memory capacity of DRAM increases about four times in three years, whereas the memory capacity required for work stations increases about two times in four years. In this context, it is conceivable that a memory device using first generation 1 M.times.1 bit DRAM packages of one-bit input/output data structure may be replaced with a memory device using second generation 4 M DRAM packages of 4-bit input/output data structure to thereby reduce the minimum memory capacity to 4 MB, or may be replaced with a memory device using third generation 16 M bit DRAM packages of 8-bit input/output data structure to thereby reduce the minimum memory capacity to 8 MB.
In this case, the memory device using the second generation IC memory packages has a high possibility of occurrence of four bit errors or less if one of the IC memory packages becomes faulty. It is necessary therefore to use SEC-DED-S4ED codes as error correcting/detecting codes. Use of these codes requires seven check bits, so the total code length becomes thirty nine bits. As a result, the memory device can be constructed using ten IC memory packages, leaving one idle bit.
Similarly, the memory device using the third generation IC memory packages of 8-bit input/output data structure has a high possibility of occurrence of eight bit errors or less if one of the IC memory packages becomes faulty. It is therefore necessary to use SEC-DED-S8ED codes as error correcting/detecting codes. Use of these codes requires ten check bits, so the total code length becomes forty two bits. As a result, the memory device can be constructed using six IC memory packages of 8-bit input/output data structure (total 48 bits), leaving six idle bits. This memory device using the third generation IC memory packages has a different total code length, posing a problem unable to retain connection compatibility with another memory device using the different generation IC memory packages, e.g., of 4-bit input/output data bit.
Apart from the above, as a means for using the common error correcting/detection code length, a memory device may be constructed of five third generation IC memory packages of 8-bit input/output data structure, with the total code length of 39 bits leaving one idle bit, to allow 7-bit error correcting/detecting codes same as the second generation to be used. However, this memory device has a problem in practical use because the multiple bit error detection factor within each 8-bit block is considerably lowered as small as 74.2%.
On the other hand, consider the case wherein the total code length of the memory device using the first generation IC memory packages of one-bit input/output data structure, or of the memory device using the second IC memory packages of 4-bit input/output data structure, is set to 42 bits, which is same as the third generation. In this case, three wasteful IC memory packages for the first generation, or one wasteful IC memory package for the second generation, is required to be used uneconomically.